vhdl语言设计数字时钟

急:EDA用VHDL语言设计多功能数字时钟...要求外加控制信号1HZ,可整点报时. 用一个计50000的计数器，当计数器为0的时候，计数器为50000，输出反向。那么输出就是1Hz 答案补充原理图很简单答案补充恩，我说一下思路，就是当你设计计数器为0，先把其画为正向，然后让计数器 反向 EDA中的数字时钟用VHDL语言怎么做 library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity dongtai is port(clk,rest:in std_logic;seg,led:out std_logic_vector(7 downto 0));end dongtai;architecture action of dongtai is signal counter,counter2,counter3,counter4,counter5,counter7,counter8,counter9:integer:=0;signal counter1:std_logic_vector(7 downto 0);begin clock:process variable tmp,tmp1,count,count2,count3,count4,count5,count7,count8,count9:integer:=0;begin wait until clk='1';tmp:=tmp+1;tmp1:=tmp1+1;if(tmp1=50000000)then count2:=count2+1;counter2;tmp1:=0;111 if(count2=10)then count2:=0;count3:=count3+1;counter3;222 if(count3=6)then count3:=0;count4:=count4+1;counter4;444 if(count4=10)then count4:=0;count5:=count5+1;counter5;555 if(count5=6)then count5:=0;count7:=count7+1;counter7;777 if(count7=10)then count7:=0;count8:=count8+1;counter8;8888 if(count8>3)then count8:=0;end if;end if;end if;end if;end if;end if;end if;if(count8=2 and count7=3 and count5=5 and ... 高分求 基于VHDL语言设计的数字时钟 -程序（.vhd文件）如下- library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;Uncomment the following library declaration if instantiating any Xilinx primitives in this code. library UNISIM;use UNISIM.VComponents.all;entity clock is port clk:in std_logic;rst:in std_logic;inc_min:in std_logic;sub_min:in std_logic;inc_hour:in std_logic;sub_hour:in std_logic;sel:out std_logic_vector(3 downto 0);q:out std_logic_vector(7 downto 0));end clock;architecture Behavioral of clock is signal sec_counter1:std_logic_vector(3 downto 0);signal sec_counter2:std_logic_vector(3 downto 0);signal min_counter1:std_logic_vector(3 downto 0);signal min_counter2:std_logic_vector(3 downto 0);signal hour_counter1:std_logic_vector(3 downto 0);signal hour_counter2:std_logic_vector(3 downto 0);signal divcounter:std_logic_vector(27 downto 0);signal div_clk:std_logic;signal scancounter:std_logic_vector(10 downto 0);signal scan_clk:std_logic;signal scan_out:std_... VHDL数字时钟完整程序代码（要求要有元件例化，并 课程设计任务书 课程设计名称 EDA课程设计 学生姓名 专业班级 设计题目 多功能数字钟设计 一、课程设计目的 1、综合运用EDA技术，独立完成一个课题的设计，考察运用所学知识，解决实际问题的能力；2、结合理论知识，考察阅读参考资料、文献、手VHDL数字时钟完整程序代码（要求要有元件例化，并 FPGA用VHDL语言写个数字时钟，为什么调时间的按键要个键扫描模块？ FPGA用VHDL语言写个数字时钟，为什么调时间的按键要个键扫描模块？因为物理按键按下后会产生一个上下抖动的波形，之后才会稳定到高或者低，一般有几十个ms，如果不加按键... 用VHDL语言制作数字时钟 1、24小时计数显示；2、具有校时功能（时，分）；附加要求： 1、实现闹钟功能（定时，闹响）；三、源代码 library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity szz is port(clk:in std_logic;clk1:in std_logic;md1:in std_logic;md2:in std_logic_vector(1 downto 0);speak:out std_logic;dout:out std_logic_vector(6 downto 0);selout:out std_logic_vector(2 downto 0));end szz;architecture one of szz is signal sel:std_logic_vector(2 downto 0);signal hou1:std_logic_vector(3 downto 0);signal hou2:std_logic_vector(3 downto 0);signal min1:std_logic_vector(3 downto 0);signal min2:std_logic_vector(3 downto 0);signal seth1:std_logic_vector(3 downto 0);signal seth2:std_logic_vector(3 downto 0);signal setm1:std_logic_vector(3 downto 0);signal setm2:std_logic_vector(3 downto 0);signal sec1:std_logic_vector(3 downto 0);signal sec2:std_logic_vector(3 downto 0);signal h1:std_logic_vector(3 downto 0);signal h2:std_logic_vector(3 downto 0);signal m1:std_logic_vector(3 downto 0);signal ... 求 EDA 的 数字时钟 程序 。 是 VHDL 语言的。 输入1Hz的时钟作为秒信号,秒计数满60后向分计数进1，分计数满60后向时计数进1。当计数到24:60:60自动回到00:00:00；library ieee;use ieee.std_logic_1164.all;entity clock is port(clk:in std_logic;输入1Hz的时钟作为秒信号 clr:in std_logic;异步清零信号 s:out integer range 0 to 60;秒 min:out integer range 0 to 60;分 h:out integer range 0 to 24-时 end clock;architecture clock of clock is begin process(clk,clr) variable count1:integer range 0 to 60;秒计数 variable count2:integer range 0 to 60;分计数 variable count3:integer range 0 to 24;时计数 begin s;min;h;if(clr='1')then count1:=0;count2:=0;count3:=0;elsif(clk'event and clk='1')then count1:=count1+1;if(count1=60)then count1:=0;count2:=count2+1;if(count2=60)then count2:=0;count3:=count3+1;if(count3=24)then count3:=0;end if;end if;end if;end if;end process;end clock; 怎样用VHDL语言设计数字钟? 是设置初始时钟吗,有一个CLK的引脚可以用. 用VHDL语言设计一个电子时钟 library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity shuzizhong is port(clk,clk1,set,change,s1,s2,s3:in std_logic;second1,second2,minite1,minite2,hour1,hour2:out std_logic_vector(3 downto 0);Light:out std_logic_vector(7 downto 0);cout:out std_logic);end entity;architecture one of shuzizhong is begin pro1:process(clk,set,s1,s2,s3,change) variable msecond1,msecond2,mminite1,mminite2,mhour11,mhour12,mhour21,mhour22:std_logic_vector(3 downto 0);begin if clk'event and clk='1' then if set='1' then-启动校验 if s1='1' then msecond1:=msecond1+1;if msecond1=\"1010 then msecond1:=\"0000;msecond2:=msecond2+1;if msecond2=\"0110 then msecond2:=\"0000;end if;end if;end if;秒校验 if s2='1' then mminite1:=mminite1+1;if mminite1=\"1010 then mminite1:=\"0000;mminite2:=mminite2+1;if mminite2=\"0110 then mminite2:=\"0000;end if;end if;end if;分校验 if s3='1' then mhour11:=mhour11+1;mhour21:=mhour21+1;if mhour11=\"1010\"then mhour11:=\"0000;mhour12:=mhour12+1;end if;if mhour11=\"0011... 用VHDL语言编写一数字时钟 library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity digital is port(Clk:in std_logic;时钟输入 Rst:in std_logic;复位输入 S1,S2:in std_logic;时间调节输入 led:out std_logic_vector(3 downto 0);整点输报时输出 spk:out std_logic;Display:out std_logic_vector(6 downto 0);七段码管显示输出 SEG_SEL:buffer std_logic_vector(2 downto 0)-七段码管扫描驱动 end digital;architecture behave of digital is signal Disp_Temp:integer range 0 to 15;signal Disp_Decode:std_logic_vector(6 downto 0);signal SEC1,SEC10:integer range 0 to 9;signal MIN1,MIN10:integer range 0 to 9;signal HOUR1,HOUR10:integer range 0 to 9;signal Clk1kHz:std_logic;数码管扫描时钟 signal Clk1Hz:std_logic;时钟计时时钟 signal led_count:std_logic_vector(2 downto 0);signal led_display:std_logic_vector(3 downto 0);signal spkcout:std_logic;begin PROCESS(clk)-产生1hz信号 variable cnt:INTEGER RANGE 0 TO 49999999;产生1Hz时钟的分频计数器 BEGIN IF clk='1' AND clk'event THEN IF cnt=...

#vhdl#fpga#vector#vhdl语言#时钟信号