利用EDA设计加法器和减法器并且附有程序代码的实验报告 library ieee；use ieee.std_logic_1164.all；use ieee.std_logic_unsigned.all；entity full isport(cin：in std_logic；a，b：in std_logic_vecter(7downto 0)；s：out std_logic_vecter(7downto 0)；cout：out std_logicend full；architecture beh of full issignal sint：std_logic_vector(8 downto 0)；signal aa，bb：std_logic_vector(8 downto 0)；beginaa(7downto 0)；bb(7downto 0)；sint；s(7 downto 0)(7 downto 0)：cout(4)；end a；这个是8位加法器library ieee；use ieee.std_logic_1164.all；use ieee.std_logic_unsigned.all；entity jfq isport(sub：in std_logic；a，b：in std_logic_vector(3 downto 0)；s：out std_logic_vector(3 downto 0)；cout：out std_logicend jfq；architecture beh of jfq issignal a1，a2，a3：std_logic(3 downto 0)；begina1(3 downto 0)；a2(3 downto 0)；a3；s(3 downto 0)；cout(3 downto 0)；end beh；这个是4未减法器
求设计个多进制加法器，是实验报告，急求！！！ 4
TEC-5实验箱中二进制补码加法器怎么做实验？ 自己好好做！要是让我知道你是谁，给你实验零分！
