vhdl语言实现8位算术逻辑运算器 library IEEE；use IEEE.STD_LOGIC_1164.ALL；use IEEE.STD_LOGIC_ARITH.ALL；use IEEE.STD_LOGIC_UNSIGNED.ALL；Uncomment the following library declaration if instantiatingany Xilinx primitives in this code.library UNISIM；use UNISIM.VComponents.all；entity minutes isPort(rst3，selector2，ky_2j：in STD_LOGIC；B10：in std_logic；C：out std_logic；dat30：out std_logic_vector(7 downto 0))；end minutes；architecture Behavioral of minutes issignal dat31，dat32：std_logic_vector(7 downto 0)：=(others=>；'0')；beginprocess(rst3，B10，ky_2j)begincase selector2 iswhen '1'=>；dat32；if ky_2j'event and ky_2j='1' thenif dat31(7 downto 4)=\"0101\"and dat31(3 downto 0)=\"1001then dat31(7 downto 0)；elsif dat31(3 downto 0)(3 downto 0)(3 downto 0)+1；else dat31(3 downto 0)；if dat31(7 downto 4)(7 downto 4)(7 downto 4)+1；else dat31(7 downto 4)；end if；end if；end if；dat30；when '0'=>；dat31；if(rst3='0')then dat32(others=>；'0')；elsif B10'event and B10='1' thenif dat32(7 downto 4)=\"0101\"and dat32(3 downto 0)=\"1001then C；dat32(7 。
用VHDL来设计一个4位算术逻辑运算单元 回去吃奶再来！
用VHDL语言编程设计4位算术逻辑单元(ALU) 做个四位串行加法器从最基本开始，减法不需要。ALU里没有减法。对减数求补（连符号位求反加1），再与被减数相加，就是做减法。还需要移位功能，这是ALU必需的。
